Contributor Index

Hirotaka Tamura received his B.S., M.S., and Ph.D. degrees in electronic engineering from Tokyo University, Tokyo, Japan in 1977, 1979, and 1982. He joined Fujitsu Laboratories in 1982. After being involved in the development of different exploratory devices such as Josephson junction devices and high-temperature superconductor devices, he moved into the field of high-speed CMOS signaling in 1996 and got involved in the development of a multi-channel high-speed I/O for server interconnects. Since then, he has been working in the area of architecture- and transistor-level design for high-speed CMOS signaling circuits. Since 2014, he has been expanding his area to cover devices, circuits, and architectures for post-Moore-era computing. He is a Fellow of the IEEE.
HPC in Asia
HPC Accelerators
Heterogeneous Systems
Parallel Algorithms
Post Moore’s Law Computing