Project Poster
(PP29): Cygnus: A Multi-Hybrid Supercomputing Platform with GPUs and FPGAs
Event Type
Project Poster
HPC Accelerators
Heterogeneous Systems
TimeTuesday, June 18th3:15pm - 3:45pm
LocationBooth N-230
DescriptionGraphics processing units (GPUs) have been widely used in high-performance computing (HPC) systems as accelerators because they can offer good peak performance and high memory bandwidth. However, the GPU is not almighty as an accelerator because it is not effective in applications that employ complicated algorithms using exception, non single-instruction-multiple-data streams (SIMD), partially poor parallelism, etc. To address these problems, field programmable gate arrays (FPGAs) have gained attention in HPC research because their computation and communication capabilities have dramatically improved in recent years as a result of improvements to semiconductor integration technologies that depend on Moore's Law. In addition to FPGA performance improvements, OpenCL-based FPGA development toolchains have been developed and offered by FPGA vendors, which reduces the programming effort required as compared to the past, and as a result, the interest in the FPGA from HPC field has been more increased. In this project, we make FPGAs cooperate with GPUs and utilize both accelerators complementarily in order to maximize the FPGA potential and to apply it to GPU-based HPC systems. We propose how to use FPGA for HPC which enables on-the-fly offloading computation at which CPUs/GPUs perform poorly to FPGAs while performing low-latency intra/inter-node communication, build a programming framework to comprehensively control these functionalities from the CPU, and demonstrate the effectiveness of our proposed approach by applying it to computational science applications.