(PhD02) Scaling Stencil Computation on OpenPOWER Near-Memory Computing Architecture
AI/Machine Learning/Deep Learning
Performance Analysis and Optimization
TimeMonday, June 17th1pm - 6pm CEST
DescriptionThe traditional processor-centric approach of computation is based on moving data through a memory hierarchy into compute units. These memory units themselves are a passive component. This processor-centric approach takes advantage of data locality, in space and time, to hide the latency and energy overhead associated with data movement. However, modern HPC workloads such as graph processing and neural networks have a random-access behavior, leading to a poor locality that greatly reduces the advantage of a processor-centric approach.
With recent advances in memory architectures, we are witnessing a paradigm shift towards a data-centric approach, where data plays a central role instead of computing. This data-centric approach consists of placing compute units close to the memory to reduce unnecessary data movement, which is referred to as near memory computing (NMC). Conceptually this approach can be applied to any level or type of memory to improve the overall system performance. However, to establish NMC as a viable solution for current HPC applications, several key challenges need to be addressed, including system integration, architectural design space exploration, data mapping, cache coherency, and virtual memory support
We have developed an NMC performance prediction framework using ensemble learning that combines hardware parameters and application-specific characteristics to provide performance estimates for previously unseen applications. This framework can provide rapid exploration compared to a state-of-the-art NMC simulator. Our current focus is on intranode scaling for weather forecasting application on POWER9 and near-memory accelerators via high bandwidth OpenCAPI interface.