Research Paper
Toward efficient architecture-independent algorithms for dynamic programs
Event Type
Research Paper
Containerized HPC
Exascale Systems
Parallel Algorithms
Parallel Applications
TimeTuesday, June 18th2:45pm - 3:15pm
LocationAnalog 1, 2
DescriptionWe argue that the recursive divide-and-conquer paradigm is highly
suited for designing algorithms to run efficiently under both shared-memory (multi- and manycores) and distributed-memory settings. The depth-first recursive decomposition of tasks and data is known to allow computations with potentially high temporal locality, and automatic adaptivity when resource availability (e.g., available space in shared caches) changes during runtime. Higher data locality leads to better intra-node I/O and cache performance and lower inter-node communication complexity, which in turn can reduce running times and energy consumption. Indeed, we show that a class of grid-based parallel recursive divide-and-conquer algorithms (for dynamic programs) can be run with provably optimal or near-optimal performance bounds on fat cores (cache complexity), thin cores (data movements), and purely distributed-memory machines (communication complexity) without changing the algorithm’s basic structure. Two-way recursive divide-and-conquer algorithms are known for solving dynamic programming problems on shared-memory multicore machines. We show how to extend them to run efficiently also on manycore GPUs and distributed-memory machines.
Our GPU algorithms work efficiently even when the data is too large to fit into the host RAM. These are external-memory algorithms based on recursive r-way divide and conquer, where r (≥ 2) varies based on the current depth of the recursion. Our distributed-memory algorithms are also based on multi-way recursive divide and conquer that extends naturally inside each shared-memory multicore/manycore compute node. We show that these algorithms are work-optimal and have low latency and bandwidth bounds. We also report empirical results for our GPU and distribute memory algorithms.