Exploring Alternative Numerical Formats Using Reconfigurable Architectures
Event Type
Focus Session
HPC Accelerators
Programming Models & Languages
TimeTuesday, June 18th9:30am - 10am CEST
LocationPanorama 3
DescriptionThe inevitable end of Moore’s law motivates researchers to re-think many of the historical architectural decisions. Among these decisions we find the representation of floating-point numbers, which has remained unchanged for nearly three decades. Chasing better performance, lower power consumption or improved accuracy, researches today are actively searching for smaller and/or better representations. Today, a multitude of different representations are found in the specialized (e.g. Deep-Learning) applications as well as for general-purpose applications (e.g. POSITs).

However, despite their claimed strengths, alternative representations remain difficult to evaluate empirically. There are software approaches and emulation libraries available, but their slowness only allows the smallest of data-sets to be evaluated and understood.

In this talk, I will show how we have described the POSIT representation using hardware description languages and embedded it into the well-known OpenCL programming model, ready to be accelerated using reconfigurable architectures. Our approach allows us to reach the performance levels required to start evaluating large workloads empirically, which will be illustrated with use-cases we have explored.