Deep Memory-Storage Hierarchy and Pace-Matching Data Access
Performance Analysis and Optimization
Post Moore’s Law Computing
TimeTuesday, June 18th8:30am - 9am
DescriptionComputing has changed from compute-centric to data-centric. From deep-learning to visualization, data access becomes the main performance concern of computing. In this talk, based on a series of fundamental results and their supporting mechanisms, we introduce a new thought on memory system design. We first present the Concurrent-AMAT (C-AMAT) data access model to quantify the unified impact of data locality, concurrency and overlapping. Then, we introduce the pace-matching data-transfer design methodology to optimize memory system performance. Based on the pace-matching design, a memory-storage hierarchy is built to generate final results and to mask the performance gap between computing and data transfer. C-AMAT is used to optimize performance at each memory layer, and a global management algorithm, named Layered Performance Matching (LPM), is developed to optimize the overall performance of the memory system. The holistic pace-matching optimization is very different from the conventional locality-based system optimization and is especially powerful in a dynamic heterogeneous environment. A deep memory-storage hierarchy system is designed to carry the pace-matching optimization. Experimental testing confirms the theoretical findings, with a 150x reduction of memory stall time. We will present the concept of the pace-matching data-transfer design and some case studies on DoE and NASA applications. We will also discuss our current NSF funded DMSH projects as well as general research issues related to advanced memory systems.