HPC in Asia
Digital Annealer: A Dedicated System for Quadratic Unconstrained Binary Optimization
Event Type
HPC in Asia
HPC Accelerators
Heterogeneous Systems
Parallel Algorithms
Post Moore’s Law Computing
TimeWednesday, June 19th11:40am - 12:10pm
LocationAnalog 1, 2
DescriptionThe Digital Annealer (DA) is a dedicated system for Quadratic Unconstrained Binary Optimization (QUBO), where a quadratic function of binary bits is minimized without constraint. As part of the DA, a chip named the Digital Annealing Unit (DAU) was developed and configured. The DAU by itself can handle up to 8k bits fully connected through 16- to 64-bit weights, while the system capacity and performance are extended beyond the chip capability. The DAU uses Markov Chain Monte Carlo as a basic search mechanism, accelerated by the use of the DAU’s hardware parallelism. The search speed is #T Metropolis-trials per second with a bit-flipping rate of ###M bit-flips per second, orders of magnitude faster than standard software solutions. For standard benchmark instances of the Quadratic Assignment Problem (QAP), the DA is up to ##,### times faster than CLPEX, a general-purpose linear solver.