Digital Annealer: A Dedicated System for Quadratic Unconstrained Binary Optimization
Event Type
HPC in Asia
HPC Accelerators
Heterogeneous Systems
Parallel Algorithms
Post Moore’s Law Computing
TimeWednesday, June 19th11:50am - 12:15pm CEST
LocationAnalog 1, 2
DescriptionWe have proposed the Digital Annealer (DA) as an option for improving computing performance after the end of Moore's law. The DA is a dedicated system for Quadratic Unconstrained Binary Optimization (QUBO), where a quadratic function of binary bits is minimized without constraint. A chip named the Digital Annealing Unit (DAU) is used as a hardware optimization engine in the DA. The current generation of the DAU can handle QUBO, in which up to 8k bits are fully connected through 16- to 64-bit weights. The DAU uses Markov Chain Monte Carlo (MCMC) as a basic search mechanism, accelerated by the use of hardware parallelism that achieves near rejection-free MCMC operation, where the state changes without a rejection for each Metropolis iteration. As an optimizer, the DAU utilizes Parallel Tempering in addition to ordinary Simulated Annealing, thus providing better solutions and ease of annealing schedule adjustment. In this talk, the design concept of the DA, the principle of the speeding-up method by parallel operation, and the benchmark results showing the effect of this method will be presented.